Programmable Logic Controllers
5th Edition
ISBN: 9780073373843
Author: Frank D. Petruzella
Publisher: McGraw-Hill Education
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Question
Chapter 1, Problem 20RQ
Program Plan Intro
Programmable Logic Controller (PLC):
- • Programmable Logic Controller (PLC) is a specialized computer used in industrial segments to control machines and process.
- • PLC is program that consists of a set of instructions which resembles the controlling functions needed to perform specific tasks.
- • The function of PLC is similar to that of a relay and hence, in an industrial segment a relay is greatly replaced by a suitable PLC.
- • When compared to general PC, a PLC is available in small and tiny sizes.
- • The basic architecture of a PLC consists of an input-output interface module and a small Central Processing Unit (CPU) that runs by control
programming language.
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Design a controller for 4-bit computer using the given table. (assume instruction register size is 10 bit)
Opcode Binary RepresentationLDA 10010ADD 10110SUB 11111OUT 01101HLT 00001
What is the key difference between programmable input/output (I/O) and interrupt-driven I/O?
Q2
Design a controller for 4-bit computer using the given table. (assume instruction register size is 10 bit)
Opcode Binary Representation
LDA 10010
ADD 10110
SUB 11111
OUT 01101
HLT 00001
Chapter 1 Solutions
Programmable Logic Controllers
Ch. 1 - Prob. 1RQCh. 1 - Identify four tasks in addition to relay switching...Ch. 1 - Prob. 3RQCh. 1 - Prob. 4RQCh. 1 - Prob. 5RQCh. 1 - Prob. 6RQCh. 1 - Explain the main function of each of the following...Ch. 1 - What are the two most common types of PLC...Ch. 1 - Prob. 9RQCh. 1 - Prob. 10RQ
Ch. 1 - Answer the following with reference to the process...Ch. 1 - Prob. 12RQCh. 1 - Answer the following with reference to the process...Ch. 1 - Prob. 14RQCh. 1 - Compare the PLC and PC with regard to: a. Physical...Ch. 1 - Prob. 16RQCh. 1 - Prob. 17RQCh. 1 - Prob. 18RQCh. 1 - Prob. 19RQCh. 1 - Prob. 20RQCh. 1 - List five factors affecting the memory size needed...Ch. 1 - Prob. 22RQCh. 1 - Given two single-pole switches, write a program...Ch. 1 - Given two single-pole switches, write a program...Ch. 1 - Prob. 3PCh. 1 - Prob. 4PCh. 1 - Prob. 5P
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- A computer system interfaces a memory with a 32-bit address bus and a 16-bit data bus. The memory addressing is performed using a decoder. What is the number of AND gates needed to implement the decoder? What is the FAN OUT of the decoder?arrow_forwardUsing four 32 x 8 ROM chips, design a circuit such that the effective size of the ROM circuit is 64 x 16. The ROM chip must show the Address inputs, enable input, and data connections. As shown in the lessons, use the MSB(s) of the combined address lines as the chip selection lines.arrow_forwardDraw a basic logic diagram for a 512 × 8-bit static RAM, showing all the inputs and outputs.arrow_forward
- Design complete hardware circuit for following 8-big register operation, X, Y, Z are register names; you can use an 8 bit bus wire where needed: X= Y-88arrow_forwardDesign a 4-bit arithmetic logic unit that can handle microprocesses defined according to the variables in the table.arrow_forwardDraw block diagram for 64k * 8 memoryarrow_forward
- The interrupt vector table is made up of many entries, each of which has its own independent data structure.arrow_forwardCategory: CPU Wiring Look at the following (incomplete) diagram of the Hack CPU taken from figure 5.9 of the textbook. ALU output outM instruction AM inM writeM A addressM inc reset PC po Match the wires A, B, C, D and E with the logic expression that describes the signal they should carry. The logic expressions use the operators not (!), and (&&) and or (I). The 16 wire instruction is named instr. The A and C instruction formats are: A-instruction: 0 V. V. V C-instruction: 1 1 1 a c1 c2 c3 c5 c6 d1 d2 d3 j1 j2 j3 Mire number: 15 14 13 12 11 10 9 8 6. 4 3 1 instr[15) && instr[3] B. instr[14] ALUarrow_forwardFor computers based On three address instruction fonnats, each adbess field can be used to specify which of the foilowing SI: A memory operand Sh A processor register S3: An implied accumulator tregisterarrow_forward
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