Subject: Computer Networks Note: Please answer in own words. copy from internet will very unhelpful for me. Question: Explain the timing diagrams of two different connection establishment mechanisms of TCP.
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Q: Subject: Computer Networks Note: Please answer in own words. copy from internet will very unhelpful…
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Subject: Computer Networks
Note: Please answer in own words. copy from internet will very unhelpful for me.
Question:
Explain the timing diagrams of two different connection establishment
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- What are MCBs? Explain the working also?Q3 /mention (3) main differences between TCP/IP AND OSI MODEL?1. A circuit with 2 or more connected transistors is called _________ or multi-staged amplification. A) Cascaded B) Inverter C) Dual amplifier D) Rectifier2. He is an Austrian-Hungarian physicist who developed the first undocumented semi-conductor device. A) Edward Howard B) Elizabeth Miles C) Morgan Sparks D) Julies Edgar Lilienfeld3. Who made the Bipolar junction? A) Daniel Levi B) John Jonson C) Mathew Wills D) Morgan Sparks
- (a)A typical TTL IC is numbered as DM54AS04N.Explain the meaning of each portion of this number?- (b) What are types of scale of integration? Briefly explain VLSI?( (c)Draw the diagram of Monostable Multivibrator using 555 timer? -Q.4: Choose the right answer for the following: 2. What is the duration of bus cycle in 8086 MPU if the clock is 20 MHz and two wait states are inserted? a- 50 nsec b-200nsec c-250nsec d- 300nsec 3. If READY pin is grounded, it will introduce -----state into the bus cycle of the 8086 MP. c- wait a- high 4. The 74ALS138 has total of ---- outputs. a- four b- 16 c- ten d-8 5. When A0-0, it makes the address an - b- no d- low address. a- I/O b- even c- odd d- extra 6. If the oscillation frequency of 8284A clock generator is 24 MHz, the clock signal frequency is----- a-4 MHz b- 20 MHz c-8 MHz d- 6 MHz 7. If the oscillation frequency of 8284A clock gererator is 24 MHz, the peripheral frequency is------ a-4 MHz b- 20 MHz c- 8 MHz d- 6 MHz 8. In fully buffered 8086 microprocessor, its address p ns are already buffered by... a- two 74LS373 address latches b- hree 74LS245 address latches c- three 74LS373 address latches 9. The RES input to the 8284A is placed at logic -- lev l in order to reset…TRUE/FALSE QUIZ 1. The de supply voltage for TTL is typically +5 V. 2. The fan-out of a logic gate is the number of gates in an IC package. 3. CMOS uses MOSFETS. 4. BJT stands for binary junction transistor. 5. An open-collector gate must be connected to an external resistor. 6. CMOS is the dominant digital IC technology. 7. A totem-pole output means that two or more resistors are in series. 8. CMOS is subject to ESD. 9. A tri-state output can be HIGH, LOW or high-impedance. 10. Propagation delay is a measure of the speed of a logic gate.
- Give proper explanation and don't copy from google or any other website Which of the following are true When switching devices are connected in series in a two-level voltage source inverter _______ a. Allows for higher voltage operation b. Needs voltage balancing during steady state and dynamic cond itions c. Improves output voltage quality d. Increases harmonic components in the output voltage waveformdraw the curcuit diagram for 4 channel 4 bit multiplexer implemented using 4 channel 1 bit multiplexer. make sure that i need full circuit to save the final multiplexer in the library.Explain what the circuit does and how it works. (Hint: This circuit is called a 2-bit synchronous binary up-down counter.)
- Answer the following questions i. ii. What is address depletion problem in IP v4 ? Due to what causes does this problem arise? ii. What are the possible solutions for such problem?1. Write the TTL level of the following voltages (low, high, intermediate). 2.5 . 0.3 . 4.6 . 1.1.. 3.2. ........ 2. .are complete circuits constructed on a chip of semiconductor material. What is the 3 common types of integrated circuits? . describes data shifted manually, .. describes data shifted automatically for 8 bit shift register. 3. How serial and parallel data shifted into 8 bit shift register?Electrical Engineering 1. Illustrate (then describe briefly): Procedure in testing the seven basic logic gates: a. AND; b. OR; c. XOR; d. NAND; e. NOR; f. XNOR; and g. the NOT. Give common faults (defects) of the seven basic logic gates. For each fault, list indicators that the gate is defective. Please completely answer the question