For this problem you are to design another sequence detector. Design constraints: 1. It must be a Moore machine. 2. The sequence it must detect in a serial string of 1s and Os at input Y is "100". 3. You may assume that the values arriving at input Y are properly synchronized with the clock. 4. The output must be Z = 1 when the prescribed sequence is detected, and 0 otherwise. 5. The circuit does not have to automatically reset when a 1 output occurs. (Return to initial state only when appropriate for sequence detection.) 6. It is possible to implement the design with only four states and two flip-flops. Since we generally do not want to implement designs that require more resources than are necessary, you MUST not use more than two flip-flops in your design. 7. Name the flip-flops A and B, and use the following state-name definitions: So (AB=00), S₁ (AB = 01), S₂ (AB = 10), S3 (AB = 11) 8. Use So for the initial state. It is up to you to decide what each of the other state-names mean with respect to the input sequence. Since you have some freedom of choice you must clearly articulate what each state-name means. See of the lecture, for example. 9. Logic must be implemented with no more than two levels and use only AND gates and OR gates (and a single inverter if you need to generate Y' from the Y input). Please submit: a) Your design for the State Graph, with documentation of what each State means (see item 8 above).
For this problem you are to design another sequence detector. Design constraints: 1. It must be a Moore machine. 2. The sequence it must detect in a serial string of 1s and Os at input Y is "100". 3. You may assume that the values arriving at input Y are properly synchronized with the clock. 4. The output must be Z = 1 when the prescribed sequence is detected, and 0 otherwise. 5. The circuit does not have to automatically reset when a 1 output occurs. (Return to initial state only when appropriate for sequence detection.) 6. It is possible to implement the design with only four states and two flip-flops. Since we generally do not want to implement designs that require more resources than are necessary, you MUST not use more than two flip-flops in your design. 7. Name the flip-flops A and B, and use the following state-name definitions: So (AB=00), S₁ (AB = 01), S₂ (AB = 10), S3 (AB = 11) 8. Use So for the initial state. It is up to you to decide what each of the other state-names mean with respect to the input sequence. Since you have some freedom of choice you must clearly articulate what each state-name means. See of the lecture, for example. 9. Logic must be implemented with no more than two levels and use only AND gates and OR gates (and a single inverter if you need to generate Y' from the Y input). Please submit: a) Your design for the State Graph, with documentation of what each State means (see item 8 above).
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
Related questions
Question
try first part plesase
Expert Solution
This question has been solved!
Explore an expertly crafted, step-by-step solution for a thorough understanding of key concepts.
This is a popular solution!
Trending now
This is a popular solution!
Step by step
Solved in 3 steps with 3 images
Knowledge Booster
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, electrical-engineering and related others by exploring similar questions and additional content below.Recommended textbooks for you