Draw the block diagram for a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers.
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- By using the design procedure for digital computers, design the following:i. Encoderii. Decoderiii. 4-bit comparatorA digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers. a. How many selection inputs are there in each multiplexer? b. What size of multiplexers are needed? c. How many multiplexers are there in the bus?the diagram on the right is for a register bank circuit that contain 8 registers. Each register is 16-bit. Theregister can read or write to one register at a time using address bus.Design the circuit and specify the width of EVERY bus.
- Q4. A common bus system which is capable of transferring 2 bits at time with number of registers are 4 each register is of 2 bit? Draw circuit diagram for this and also define how many multiplexers are required and what will be the size of multiplexer with truth table Also explain how to gather data from this bus back into register [10]e example to each one of application of microprocess.. 2/ Write the contents of flag register after execute the following operation (AC)16 + (3B)16-8085 microprocessor went through its manipulation operation in the ALU, the results was transferred on the data bus and status of the results was stored in the flag register for indications . With your knowledge and understanding illustrate a complete bit configuration of 8085 flag register and show the functions of the represented bits in the register.
- a) What is the size of ROM? b) What kind of decoder do we need?c) Draw the circuit on paper without any wrong.RISC processors use ___________, unlike Intel processors. A) Checksum B) Peripheral I/O C) Interrupts D) Memory-mapped I/OA microprocessor has an increment memory direct instruction, which adds 1 to the value in memory location. The instruction has five stages: fetch opcode (four bus clock cycles); fetch operand address (three bus clock cyles); fetch operand (three bus clock cyles); add 1 to operand (three bus clock cyles); and, store operand (three bus clock cyles). By what amount (in percent) will the duration of the instruction increase if we have to insert two bus wait states in each memory read and memory write operation? Repeat assuming that the increment operation takes 13 cycles instead of 3 cycles.
- please show work included 4. If a 6-bit binary number is used to represent an analog value in the range from -63 to 126, what is the accuracy of the system? In other words, if the binary number is incremented by one, how much change does it represent in the analog value?The upper 16-bits of the 40-bit binary count value are displayed on the four seven-segment displays as four hexadecimal digits. Hexadecimal values aren't good for human perception. How would you suggest the counter design be modified so that only decimal count values are displayed?Write a Verilog code for 8-bit up/down counter for any type of Modeling.