Consider the following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers (see image 1). Assume the use of a four-stage pipeline: fetch, decode/issue, execute, write back. Assume that all pipeline stages take one clock cycle except for the execute stage. For simple integer arithmetic and logical instructions, the execute stage takes one cycle, but for a LOAD from memory, five cycles are consumed in the execute stage. If we have a simple scalar pipeline but allow out-of-order execution, we can construct the following table for the execution of the first seven instructions (see image 2). The entries under the four pipeline stages indicate the clock cycle at which each instruction begins each phase. In this program, the second ADD instruction (instruction 3) depends on the LOAD instruction (instruction 1) for one of its operands, r6. Because the LOAD instruction takes five clock cycles, and the issue logic encounters the dependent ADD instruction after two clocks, the issue logic must delay the ADD instruction for three clock cycles. With an out-of- order capability, the processor can stall instruction 3 at clock cycle 4, and then move on to issue the following three independent instructions, which enter execution at clocks 6, 8, and 9. The LOAD finishes execution at clock 9, and so the dependent ADD can be launched into execution on clock 10. Complete the table in imag
Consider the following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers (see image 1).
Assume the use of a four-stage pipeline: fetch, decode/issue, execute, write back. Assume that all pipeline stages take one clock cycle except for the execute stage. For simple integer arithmetic and logical instructions, the execute stage takes one cycle, but for a LOAD from memory, five cycles are consumed in the execute stage.
If we have a simple scalar pipeline but allow out-of-order execution, we can construct the following table for the execution of the first seven instructions (see image 2).
The entries under the four pipeline stages indicate the clock cycle at which each instruction begins each phase. In this program, the second ADD instruction (instruction 3) depends on the LOAD instruction (instruction 1) for one of its operands, r6. Because the LOAD instruction takes five clock cycles, and the issue logic encounters the dependent ADD instruction after two clocks, the issue logic must delay the ADD instruction for three clock cycles. With an out-of- order capability, the processor can stall instruction 3 at clock cycle 4, and then move on to issue the following three independent instructions, which enter execution at clocks 6, 8, and 9. The LOAD finishes execution at clock 9, and so the dependent ADD can be launched into execution on clock 10.
Complete the table in image 2.
![R3, R1, R2
R6, [R3]
ADD
1
LOAD
R7, R5, 3
R1, R6, R7
R7, R0, 8
2
AND
ADD
4
SRL
Image 1
R2, R4, R7
R5, R3, R4
R0, R1,
R6, [R5]
R2, R1,
OR
6
SUB
7
ADD
10
8.
LOAD
SUB
R6
10
AND
R3, R7, 15](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F306a4b4b-6a04-4894-8a41-9e2fa43dc391%2Ffc47fe6f-94b7-46c2-b6b2-95f61c4f1eec%2Fpz8pns_processed.png&w=3840&q=75)
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