6.6 Design a four-bit shift register (not a universal shift register) with parallel load using D flip-flops. (See Figs. 6.2 and Fig. 6.3.) There are two control inputs: shift and load. When shift=1, the content of the register is shifted toward A3 by one position. New data are transferred into the register when load=1 and shift=0. If both control inputs are equal to 0, the content of the register does not change. (HDL―see Problem 6.35(c), (d))
6.6 Design a four-bit shift register (not a universal shift register) with parallel load using D flip-flops. (See Figs. 6.2 and Fig. 6.3.) There are two control inputs: shift and load. When shift=1, the content of the register is shifted toward A3 by one position. New data are transferred into the register when load=1 and shift=0. If both control inputs are equal to 0, the content of the register does not change. (HDL―see Problem 6.35(c), (d))
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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