2- Construct a full-Adder logic circuit by using NAND gates only. 3- Construct a full- Subtractor logic circuit by using NOR gates only. 4- Construct a full-Adder logic circuit by using NOR gates only.
Q: An open wire T-L with G
A: Given data G=0.29*10^(-6) mho/km L=3.52 mH/km c=8.7 nF/km…
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Q: 2. In the emitter follower discussed in the lectures, the output (emitter) voltage is 0.7V below the…
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Q: Example3/ An open wire T-L with G=0.29x 10-6U/Km ,L=3.52 mH/Km, C=8.7 nF/Km ,R=6.74 KQ/Km at F=1 KHZ…
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Q: 3. Using mesh Analysis. Find the value of I, I, and I, 2-j3 4-3
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Q: Applying superposition theorem
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Q: 2. In the emitter follower discussed in the lectures, the output (emitter) voltage is 0.7V below the…
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Q: Example3/ An open wire T-L with G=0.29x 10-6U/Km ,L=3.52 mH/Km , C=8.7 nF/Km ,R=6.74 KQ/Km at F=1…
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Q: Q1/A sinusoidal voltage is generated by 85 turn coil, of dimension 20 cm by 16 cm. The coil is…
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Q: R5=1k Yb R7=1k R9=1k +YR5- R6 R8 V1 5V V2 10V 3.3k 3.3k Figure 5.2
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Q: Example1/ An open wire T-L with R=10 KN/Km ,L=3.7 mH/km, C=8.3x 10-°F/Km and G=0.4x 10-6U/Km , find…
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Q: R + G, G2 G, G4 H H
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- Draw the logic diagram and transistor implementation for a (2-2-2) AOI.1E. Write a VHDL code for all Logic Gates and verify Output waveforms. 2E. Write a VHDL code for Half Adder and verify Output waveforms. 3E. Write a VHDL code for Full Adder and verify Output waveforms.d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.
- 4) Draw a logic diagram of a divide-by-14 counter using IC 7493 and 2-input AND gate.A d. B Figure 1 3. Referring to the logic circuit in Figure 1, determine: a. The simplified Boolean expression. b. The output waveform. C H c. Due to fabrication errors, lines d and f were shorted to the supply voltage. What happens to the output of the circuit? d. Your hardware resources are limited to 2-input NOR gate only. Draw the gate schematic of the simplified Boolean expression in 3(a).Q5. Design a decoder to convert the 421 BCD codes to drive a 7-segment LEDS that displays the patterns as shown in Figure Q5. Show the design and working steps in implementing your design using NOR gate ONLY in ONE logic diagram. 1 2 3 f off = '0' on = '1' d 4 5 6
- Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- Cin Cout Figure Q4(a)(ii)Q4(a) Adder is divided into three types which are half adder, full adder, and parallel adder. Illustrate the implementation of full adder using half adder with necessary logic gates. (i) (ii) Figure Q4(a)(ii) shows the input timing diagram for a full adder. Illustrate the timing diagrams for output S and Cout- B Cin Cout Figure Q4(a)(ii) (iii) Given A = 111001 and B = 100010. Construct a 6-bit parallel adder to solve for A + B.6. i) For the circuit shown in Figure Q16, Find the logic functions of X and Y Figure Q1 ii) Simplify X and Y using Boolean algebra. hp ort delete
- 5- Determine an alternative method for implement the full-adder. Hint: Write the expressions of the circuit and simplify using icarnaugh map.Then implement using AND-OR gates. 6- Design a logic cct using NAND gate and convert BCD code to Excess-3code.We want to design a circuit to detect prime numbers.The input of the circuit is a 4-bit binary number and the output is a single bit and should show one when the number is prime and zero otherwise.B. Implement the circuit using a 4× 1 multiplexer and combinational logic gates.C. Implement the circuit using only one decoder and one OR gate. What is the size of the decoder you use?a) Design a combinational circuit that would take a 3-bit binary number and generate an output if the input value in decimal is either divisible by 2 or 3. iii) Explain and show how you would implement this circuit using a 4-to-1 Multiplexer and other appropriate logic gates. Use a block diagram for the multiplexer.