-. Using a uniform-tree network with nMOS each of the switching functions: (a) f(w,r,y.z)=w (r+y+2) (b) f(w,r,y,z) = (w.x)+ (y 2)
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- The numbers from 0-9 and a no characters is the Basic 1 digit seven segment display * .can show False True In a (CA) method of 7 segments, the anodes of all the LED segments are * "connected to the logic "O False True Some times may run out of pins on your Arduino board and need to not extend it * .with shift registers True FalseElectrical Engineering 3. For the logic circuit in Figure 1, compute the following parameters: A) The total number of single stuck-at faults. B) The total number of all possible multiple stuck-at fault combinations. C) The total number of stuck-open faults. Note: You can assume that 3-input AND gate is realized using 8 transistors, a two-input OR gate is realized using 6 transistors, and an inverter is realized using 2 transistors.d) Draw the schematics of 4-bit synchronous and asynchronous MOD-8 counters and comment on their pros and cons. e) Calculate the noise margin for a logic gate with the following logic levels: VIL = 1.1 V, VIH = 3.2 V, VOL = 0.6 V, VOH = 4.0 V.
- Implement the function, W using ONE 4-to-1 multiplexer and other logic gates. b) Implement the function, X using ONE 4-to-1 multiplexer and other logic gates. Implement the function, Y using TWO 4-to-1 multiplexer and other logic gates. d) Implement the function, Z using ONE 8-to-1 multiplexer and other logic gates. Table Q1 ВCD Braille A B D W Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A ololOConsider Lookahead Carry Generator circuit . Show how to implement this circuit using minimum number of 4x1 multiplexers and (any number of) inverters (NOT gates). Explain your solution. (you can use logic-1 and logic-0 inputs in your design, if necessary).An X-input exclusive-OR gate and a Y-input exclusive-OR gate (where X=3, Y=4 have their outputs connected to a 2-input exclusive-NORgate. Do the following:a) Draw the logic diagram and analyze the logic expression of the output (in standard SOPform).b) List out all essential prime implicants.
- Q5. Design a decoder to convert the 421 BCD codes to drive a 7-segment LEDS that displays the patterns as shown in Figure Q5. Show the design and working steps in implementing your design using NOR gate ONLY in ONE logic diagram. 1 2 3 f off = '0' on = '1' d 4 5 6Simplify the following logic function using Quine-McCluskey method (tabulation method). Then draw the simplified circuit F(A,B,C,D)=(0,2,3,5,7,11,15)=(4,6,8,12,13,14) Terms 1,9,10 are don't caredraw the implementation of the fnction Q = X+ Y as logic circuit using 4x1 Multiplexer below (with depicting the internal structures). Indicate the input and output values on each connection. (The circuit can be drawn horizontally.)
- For the basic TTL gate shown in figure (5), if all the inputs are high at logic (1), BR = 0.02 and Br = 100, then find the value of: Note: (Write the equations of each point not just the value) 1) IB2 = Amperes. 2) Vc2=1 3) Ic2= Amperes. 4) IIKQ = 5) IB3 = Amperes. 6) Ic3 = Amperes. Volt. Amperes. Figure (5) 1.4k 4k 0₂ Ya) Design a combinational circuit that would take a 3-bit binary number and generate an output if the input value in decimal is either divisible by 2 or 3. iii) Explain and show how you would implement this circuit using a 4-to-1 Multiplexer and other appropriate logic gates. Use a block diagram for the multiplexer.(b) For a gated S-R latch. determine the Q output for the inputs in the following Figure. Show it in proper relation to the enable input, also draw the input waveforms on your answer script. Assume that Q starts LOW. EN S R Minimize the combinational logic circuit in the following figure using Karnaugh's map only. Inverters for the complemented variables are not shown. Q2.