For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively add x30, x28, x29 sli x4, x30, 2 add x3, x4, x10 add x2, x4, x11 1w x30, 0(x3) 1w x31, 0(x2) sub x3, x30, x31 sw x3, 8(x10)

For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively add x30, x28, x29 sli x4, x30, 2 add x3, x4, x10 add x2, x4, x11 1w x30, 0(x3) 1w x31, 0(x2) sub x3, x30, x31 sw x3, 8(x10)

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 12VE

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For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and 3 are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and 11, respectively. sub x30, x28, x29 slli x30, x30, 2 add x3, x30, x10 add x4, x30, x11 Iw x30, 0(x3) 1w x31, 0(x4) add x30, x30, x31 sw x30, 16 (x11)
For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively: sub x30, x28, x29 slli x30, x30, 2 add x3, x30, x10 add x4, x30, x11 lw x30, 0 (x3) 1w x31, 0 (x4) add x30, x30, x31 sw x30, 16 (x11)
For the RISC-V assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers x5, x6, x7, x28, and x29, respectively. Assume that the base address of the arrays A and B are in registers x10 and x11, respectively. sub x30, x28, x29 slli x30, x30, 2 add x3, x30, x10 add x4, x30, x11 1w x30, 0 (x3) 1w x31, 0 (x4) add x30, x30, x31 sw x30, 16 (x11)
Consider a RISC-V assembly function func1. func1 has three passing arguments stored in registers a0, a1 and a2, uses temporary registers t0-t3 and saved registers s4–s10. func1 needs to call func2 and other functions may call func1 func2 has two passing arguments stored in registers a0 and a1, respectively. In func1, after the program returns to func1 from func2, the code needs the original values stored in registers t1 and a0 before it calls func2. How many words are the stack frames of function func1? Indicate which registers are stored on the stack of func1? pseudo-instructions are not allowed except “j target_label” and “jr ra”.
For the MIPS assembly instructions below, what is thecorresponding C statement? Assume that the variables f, g, h, i, and j areassigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume thatthe base address of the arrays A and B are in registers $s6 and $s7,respectively. Note: for each line of MIPS code below, write the respective Ccode. After that, write the corresponding C code for the MIPS.sll $t0, $s0, 2add $t0, $s6sll $t1, $s1, 2 add $t1, $s7, $t1lw $s0, 0($t0)addi $t2, $t0, 4lw $t0, 0($t2)add $t0, $t0, $s0sw $t0, 0($t1)
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Tompute the physical address for the specified operand in each of the following instructions. egister contents and variable are as follows: (CS)=0A00H, (DS)=OB0OH, (SS)=OD00H, S)=OFFOH, (DI)=00BOH, (BP)=00EAH and (UP)=0000H, LIST=00FOH, AX=4020H, BX=2500H. 1) Destination operand of the instruction MOV LIST (BP+DI], AX 2) Source operand of the instruction MOV CL, [BX+200H] 3) Destination operand of the instruction MOV [DI+6400H], DX 4) Source operand of the instruction MOV AL, [BP+SI-400H] 5) Destination operand of the instruction MOV [DI+SP], AX 6) Source operand of the instruction MOV CL, [SP+200H] 7) Destination operand of the instruction MOV [BX+DI+6400H], CX 8) Source operand of the instruction MOV AL , [BP-0200H] 9) Destination operand of the instruction MOV [SI], AX 10) Destination operand of the instruction MOV [BX][DI]+0400H,AL 11) Source operand of the instruction MOV AX, [BP+200H] 12) Source operand of the instruction MOV AL, [SI-0100H] 13) Destination operand of the…
Assume that the instruction pointer, EIP, contains 9810 and the assembly language representation of the instruction in memory at address 9810 is JAE 131. If the flags are currently CF=1, ZF=0 and SF=0 what is the value of the EIP after the instruction executes? The answer 102 is not correct so what is the correct answer?
Determine the value in LR (R14) and PC (R15) when microprocessor is executing theinstruction in Line 21 (SUBS R0, R0, #0x05).
Assume that the instruction pointer, EIP, contains 10410 and the assembly language representation of the instruction in memory at address 10410 is JNE 59. If the flags are currently CF=1, ZF=0 and SF=1 what is the value of the EIP after the instruction executes?